clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock
authorBoris Brezillon <boris.brezillon@free-electrons.com>
Thu, 1 Dec 2016 21:00:20 +0000 (22:00 +0100)
committerpopcornmix <popcornmix@gmail.com>
Mon, 20 Feb 2017 20:31:34 +0000 (20:31 +0000)
commit84297af8104d14bf30d41ec23e48e353aeaee604
treef89bf2890cea57d3fce6f322de4ff060a6246a39
parent42e34c9734335229cab7a879c73c9d1c24b186cb
clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock

The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
(cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd)
drivers/clk/bcm/clk-bcm2835.c